Abstract
CMOS Static Random Access Memories (SRAMs) are widely used for In-Memory Computing (IMC) in modern systems to achieve fast and efficient logic and arithmetic computations. However, aging, such as BTI, is a serious threat to the reliability of the SRAMs operations, affecting also significantly the results of the IMC operations in these memories. Hence, it is crucial to develop aging mitigation strategies to maintain the reliability of the memory. The current work proposes an aging alleviation technique for 8T CMOS SRAMs that are frequently used for IMC, by adopting a special purpose and commonly exploited in conventional 8T SRAMs source line, with proper voltage bias on it during non-active periods, as an effective solution to mitigate aging.
