Abstract
The design and verification of three floating-point components (division, reciprocal, inverse square root), based on the Sweeney, Robertson and Tocher (SRT) algorithm and implemented in SystemVerilog, that operate with up to three pipeline stages are presented. The design flow for these blocks utilizes the Genus tool from Cadence for synthesis. To ensure proper functionality, Chipware components provided by Cadence serve as a golden reference and a means of validating the correctness of the blocks. A SystemVerilog testbench is developed, instantiating the designed SRT components as well as the respective Chipware components, enabling comprehensive functional testing across various rounding modes and precisions. While the components are specifically designed to support half, single, and bfloat16 precisions, they are also adaptable to custom precisions. The functional correctness of the components is evaluated through coverage analysis using the Integrated Metrics Center (IMC) of the Xcelium tool, achieving industry-level toggle, block, and expression coverage for all parameter combinations. Furthermore, equivalency checking is performed using the Conformal tool during different synthesis stages. Power consumption results are obtained using Joules.
