A Low Power FPGA Implementation of LDPC Encoder for Space Applications

Abstract

The emergence of 5G, 6G technologies and the expanding Internet of Things (IoT) necessitate advanced data encoding techniques, with Low-Density Parity-Check (LDPC) codes being particularly notable for the high error correction efficiency and low computational complexity. An LDPC encoder with a 4/5 data rate, as specified in CCSDS standards is developed in this work, tailored for transmitting scientific data from a nano-satellite to a ground station. Implemented in SystemVerilog and designed for FPGA deployment, the encoder employs a streaming architecture and the AXI4 Stream protocol for communication interfaces. The resulting solution aims lower power consumption while demonstrating good resource utilization and throughput performance.