Fractional-N Phase Locked Loop for Wi-Fi 6/6E With 135 mW Power Consumption and Spur Reduction Techniques

Abstract

This paper presents a fractional-N phase locked loop (PLL) for Wi-Fi 6/6E applications in 28 nm FD-SOI CMOS technology. The PLL consists of an LC voltage-controlled oscillator (VCO), a dual edge phase-frequency detector (PFD), a programmable charge pump with linearization scheme, a prescaler, a fully integrated low pass filter and a 3rd order Sigma-Delta modulator to control a programmable divider. Notable features include fast automatic frequency locking, and optimal loop bandwidth (LBW) and VCO amplitude calibration. The PLL draws current from a 1.8 V supply, having a power consumption of 135 mW. The reference clock is 60 MHz, RMS jitter is 161.9 fs (1 kHz – 100 MHz) and the reference spur level is -55 dBc.