Abstract
This paper outlines a detailed design methodology for Low-Noise Amplifiers (LNAs), using a 65nm CMOS process node. The main target of this work is to simplify and accelerate the LNA design cycle without compromising on performance. The provided simulation results confirm the efficacy of the proposed methodology, deriving an LNA with S11<-30dB, S21>15dB, S12<-30dB, S22<-10dB, NF<3dB, at the specified frequency of 5 GHz.
